Analog Mixed-Signal Modelling Engineer (PHY + SerDes + Logic Timing) 5 days ago Full Time Toronto, ON Posted 5 days ago Marvell Title of the Job: Analog Mixed-Signal Modelling Engineer (PHY + SerDes + Logic Timing) Location: Toronto, ON Job Description: concepts in digital logic design Concepts digital logic timing analysis Verilog/VHDL coding and Lint tools Highly… Company Name: Marvell Salary: Apply for the job! Related Jobs:Digital IC Design, Staff EngineerStage en génie électrique - Hiver 2025 / Electrical…FPGA DeveloperCUPE-Hiver/Winter 2025- AE/TA-ELG4912WAnalog Layout EngineerAnalog Mixed Signal Design Engineer, Senior PrincipalAnalog IC Design, Staff EngineerAnalog/mixed-signal IC Modeling Engineer - AcaciaCryptographic Module Tester III - Ottawa, ONAnalog Design Engineer Intern